PXF4333 Datasheet, PDF (215/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Register Description
’1’
The queue is always scheduled/re-scheduled with its
specific rate independent of the queue filling level.
Scheduling an empty queue results in an ’empty cell
cycle’ (no cell is emitted during this cycle).
A so called ’dummy queue’ is used for generating empty
cell cycles.
Note: ’RSall’ can be set with connection setup (together
with QIDvalid=’1’) or anytime while the queue is
enabled.
After setting bit ’RSall’, the ABM-3G will
automatically set bit ’MGconf/DQsch’ to
acknowledge the first dummy schedule event.
The ’RSall’ information is internally conveyed to
the scheduler. This process is acknowledged by
an interrupt (Bit ’UDQRD/DDQRD’ in Register
103: ISRC). It is recommended not to select any
other table or table entry while waiting for this
acknowledge.
Note: ’RSall’ can be reset anytime while the queue is
enabled. In response to resetting ’RSall’ the
ABM-3G will generate an interrupt (Bit ’UDQRD/
DDQRD’ in Register 103: ISRC) and reset bit
’MGconf/DQsch’ in this table.
Note: To activate or deactivate a dummy queue, command bit
’DQac’ must be set in conjunction with setting or resetting bit
’RSall’.
QIDvalid
Queue Enable:
Data Sheet
215
2001-12-17