PXF4333 Datasheet, PDF (21/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Overview
• Optional queue sharing
• Guaranteed per-queue minimum buffer reservation
• Cell acceptance based on programmable threshold sets with hysteresis evaluation
• Threshold sets for individual queues, traffic classes, schedulers, and global buffer for
optimized buffer sharing
• Per VC Packet Discard, including Early Packet Discard (EPD) & Partial Packet
Discard (PPD) thresholds for Guaranteed Frame Rate (GFR) support
• Cell Loss Priority (CLP) aware selective discard thresholds
• UTOPIA input port backpressure thresholds without head-of-line-blocking
1.1.2 Scheduling Functions
• Multistage scheduling units with
– Work conservative Weighted Round Robin (WRR) scheduling stage for 128
Scheduler Blocks
– Each Scheduler Block comprising of
– a Weighted Fair Queueing (WFQ) scheduler with 16320 programmable weight
factors for each queue, providing rate guarantees and fairness in bandwidth
allocation
– a high priority Round Robin (RR) scheduler for real-time traffic
– a low priority RR scheduler for best effort traffic
• Additional common real-time bypass queue for each direction, for cascading multiple
ABM-3Gs
• Selectable Peak Cell Rate (PCR) shaping for each queue with minimum 2.62 Kbps
and maximum 343 Mbit/s at 52 MHz clock (65472 programmable rates)
• Selectable Variable Bit Rate (VBR.1.2.3) leaky bucket shaping for up to 2046 queues
• VC merge function for up to 128 merge groups (arbitrary queues per merge group) for
Multi Protocol Label Switching (MPLS) applications
• SB scheduler overbooking possibility
1.1.3 Interfaces
• Two external SDRAM Interfaces for cell storage, one for upstream and one for
downstream direction (up to 256 K cell buffer per direction)
• One common cell pointer SSRAM Interface
• Multiport UTOPIA Level 2 Interface in up- and downstream direction conforming to the
specifications of the ATM Forum [4]
– 4-cell FIFO buffer at UTOPIA receive interfaces for clock synchronization
(head-of-line blocking-free)
– 64-cell buffer logical queueing for up to 48 PHYs at UTOPIA transmit interfaces
(head-of-line blocking-free)
• 16-bit Microprocessor Interface, configurable as Intel or Motorola type (with AAL5
packet insertion/extraction support)
Data Sheet
21
2001-12-17