PXF4333 Datasheet, PDF (287/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

7.2.22 PLL Control Registers
Register 92 PLL1CONF
PLL1 Configuration Register
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
PLL1CONF D7_H
Written and Read by CPU
Bit
15
14
13
12
Locked1 Div2En1 Div1En1 BYPAS
S1
11
PU1
10
RES1
Bit
7
6
5
4
3
2
M1(1:0)
N1(5:0)
9
8
M1(3:2)
1
0
DPLL1 generates a clock that is an alternative clock source for the ABM-3G. The DPLL1
is fed by clock input signal ‘SYSCLK’. Signal ‘SYSCLKSEL’ determines the clock source
of the ABM-3G. Section 3.2.5 “Clocking System” on Page 52 provides the details.
Locked1
DPLL1 Locked
(read only)
1
DPLL1 is locked based on the current parameter
setting.
0
DPLL1 is in transient status.
Div2En1
Division Factor 2 Enable for DPLL1
This bit enables one of the additional divide by 2 factors subsequent
to the DPLL1 output.
0
Division Factor 2 disabled.
1
Division Factor 2 enabled.
Div1En1
Division Factor 1 Enable for DPLL1
This bit enables one of the additional divide by 2 factors subsequent
to the DPLL1 output.
Data Sheet
287
2001-12-17