PXF4333 Datasheet, PDF (230/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

7.2.12 Merge Group Table Transfer Registers
ABM-3G
PXF 4333 V1.1
Register Description
Internal Table 5: Merge Group Table Transfer Registers MGT0..MGT2
The Merge Group Table Transfer Registers are used to access the internal Merge Group
Table (MGT) containing 2*128 entries of 48 bit each. Table 7-10 shows an overview of
the registers involved.
Table 7-12 Registers for MGT Table Access
47
0
MGT RAM entry
15
0 15
0 15
0
MGT2
MGT1
MGT0
15
0 15
0 15
0
MASK2
MASK1
MASK0
RAM Select:
15
0
MAR=07_H
Entry select:
15
0
WAR (0..255_D)
MGT0..MGT2 are the transfer registers for one 48-bit MGT table entry. The Scheduler
Block number representing the table entry which needs to be read or written must be
written to the Word Address Register (WAR). The dedicated MGT table entry is read into
the MGT0..MGT2 Registers or modified by the MGT0..MGT2 register values with a write
mechanism. The associated Mask Registers MASK0..MASK2 allow a bit-wise Write
operation (0 - unmasked, 1 - masked). In case of read operation, the dedicated
MGT0..MGT2 register bit will be overwritten by the respective MGT table entry bit value.
In case of Write operation, the dedicated MGT0..MGT2 register bit will modify the
respective MGT table entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to
select the MGT table, bit field MAR(4:0) must be set to 6. Bit 5 of MAR starts the transfer
and is automatically cleared after execution.
Data Sheet
230
2001-12-17