PXF4333 Datasheet, PDF (258/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Register Description
Table 7-21 Registers SCTI Downstream Table Access
31
0
SCTI RAM Entry
(Downstream)
RAM/Entry/Word
select:
15
0
15
0
DSCTI
DSADR
(WSEL=1)
15
0
DSCTI
15
0
DSADR
(WSEL=0)
USCTI and DSCTI are the transfer registers for the 32-bit SCTI upstream/downstream
table entries. The upstream and downstream Schedulers use different tables (internal
RAM) addressed via dedicated registers, USADR/DSADR. The address registers select
the scheduler-specific entry as well as the high or low word of a 32-bit entry to be
accessed. Further, there is no command bit, but transfers are triggered via Write access
of the address registers and the data registers:
• To initiate a Read access, the Scheduler Block number must be written to the address
register USADR (upstream) or to the address register DSADR (downstream). One
system clock cycle later, the data can be Read from the respective transfer register
USCTI or DSCTI.
• To initiate a Write access, it is sufficient to Write the desired Scheduler Block number
to the address registers, USADR and DSADR, and then Write the desired data to the
respective transfer register, USCTI or DSCTI, respectively. The transfer to the integer
table is executed one system clock cycle after the Write access to USCTI or DSCTI.
Thus, consecutive Write cycles may be executed by the microprocessor.
The SCTI table entries are either read or written. Thus, no additional mask registers are
provided for bit-wise control of table entry accesses.
Data Sheet
258
2001-12-17