PXF4333 Datasheet, PDF (303/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 103 ISRC
Interrupt Status Register Common
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
ISRC
E5_H
Read by CPU to evaluate interrupt events related to both
cores. Interrupt indications must be cleared by writing a
1 to the respective bit locations; writing a 0 has no effect;
Bit
15
14
13
12
11
10
9
8
Unused(10:3)
Bit
7
6
5
4
3
2
1
0
Unused(2:0)
RAMER DDQRD UDQRD ^DQ
UQ
VCMGD VCMGD
RAMER
Configuration of common Cell Pointer RAM has been changed after
cells have been received (see Register MODE1, bit field CPR).
DDQRD
Downstream Dummy Queue Relogged/Deactivated
This interrupt confirms the dummy queue operation being activated
and deactivated. (see Register 38: QCT1)
UDQRD
Upstream Dummy Queue Relogged/Deactivated
This interrupt confirms the dummy queue operation being activated
and deactivated. (see Register 38: QCT1)
DQVCMGD
Downstream Queue VC-Merge Group Deactivated
This interrupt confirms the VC-Merge group being deactivated.
UQVCMGD
Upstream Queue VC-Merge Group Deactivated
This interrupt confirms the VC-Merge group being deactivated.
Data Sheet
303
2001-12-17