PXF4333 Datasheet, PDF (54/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Functional Description
• Clock supply: 52 MHz at signal SYSCLK
In this example, signal SYSCLKSEL must be connected to V_SS to connect the internal
core clock to the DPLL1 output. (Please refer to Figure 3-7)
DPLL1 Programming
A reasonable value for parameter M1 in register “PLL1CONF” on Page 287 is M1 = 12
which results in
f₁ = 52 MHz / (12 + 1) = 4 MHz.
Now a possible value for parameter N1 is N1 = 25 which results in
f₂ = 4 MHz * (25 + 1) = 104 MHz.
To achieve the 52 MHz core clock division factor 1 shall be enabled.
Thus, for this example the value 3B19_H must be programmed to register PLL1CONF.
The conditions given above are met because f₁=4 MHz is in the range of 2..6 MHz
(n=25) and f₂=104 MHz is between 100 and 200 MHz.
Note: Multiple combinations of parameters are possible to achieve a 52 MHz clock in
this example.
3.2.5.4 Initialization Phase
After power-on reset, the DPLL is in bypass mode which means that signal ‘SYSCLK’ is
directly feeding the internal core clock. After basic configuration of at least the DPLL
configuration registers, the bypass can be disabled which will make a glitch-free
adjustment of the internal clocks to the selected frequency.
3.2.6 Reset System
The ABM-3G provides three different reset sources, as shown in Figure 3-9. The
hardware signal RESET affects the entire device. The self-clearing software reset bit
‘SWRES’ in register “MODE1” on Page 312 also affects the entire device.
Hardware reset as well as software reset bit ‘SWRES’ completely initialize the device
into power-on reset state.
Data Sheet
54
2001-12-17