PXF4333 Datasheet, PDF (44/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

•
687 Mbit/s
(53 Byte,
51.84 MHz)
ABM-3G
PXF 4333 V1.1
Functional Description
14
42
Test/ SSRAM _ARC
Clocks
IF
50
SDRAM Interface (up)
Cell Handler upstream
687 Mbit/s
(53 byte,
51.84MHz)
64
687 Mbit/s
(53 byte,
51.84MHz)
AAL5
BSCAN _{uP IF}
5
32
Buffer
Manager
Queue
Scheduler
Cell Handler downstream
SDRAM Interface (dn)
50
ARC
64
687 Mbit/s
(53 Byte,
51.84 MHz)
Figure 3-2 Functional Block Diagram
Figure 3-3 shows a logical illustration of the ATM Buffer Manager (ABM-3G) core for one
direction.
Cells are assigned to queues in the Buffer Manager unit. The cell acceptance algorithm
verifies that no thresholds are exceeded that are provided for queues, schedulers, traffic
classes, as well as for the global buffer. Once accepted, a cell cannot be lost, but will be
emitted at the respective UTOPIA Interface after some time (exception: queue has been
disabled while cells are stored). Alternatively, cells can be received from the
Microprocessor Interface via the AAL5 unit. The demultiplexer forwards the cells to the
respective queue associated with a scheduler which sorts them for transmission
according to the programmed configuration. As part of the scheduling function, an
optional Peak Rate Limiter and a Leaky-Bucket shaper are provided for the shaping of
individual queues (connections).
The Queue Scheduler and the Buffer Manager are the key units for QoS provisioning in
the ABM-3G. The behavior of both units is described in subsequent chapters. The output
multiplexer recombines the cell streams of all schedulers. Emitted cells are either
forwarded to the UTOPIA Transmit Interface or to the AAL5 unit for extraction.
Data Sheet
44
2001-12-17