PXF4333 Datasheet, PDF (307/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

7.2.26 RAM Select Registers
Register 107 MAR
Memory Address Register
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
MAR
EB_H
Written by CPU to address internal RAM/tables for Read
or Write operation via transfer registers
Bit
15
14
13
12
11
10
9
8
Unused(9:2)
Bit
7
6
5
4
3
2
1
0
Unused Start_W Start_R
MAR(4:0)
Start_W
Start_R
MAR(4:0)
This command bit starts the Write procedure to the internal RAM/
table addressed by bit field MAR(4:0). The specific data transfer
and mask registers must be prepared appropriately in advance.
This bit is automatically cleared after completion of the Write
procedure.
Simplifies Read access without need to touch the mask registers
Memory Address
This bit field selects one of the internal RAM/tables for Read or
Write operation:
00000 LCI: LCI Table RAM (see page 191)
00001 TCT: Traffic Class Table (see page 195)
00010 QCT: Queue Configuration Table (see page 211)
00011
SBOC: Scheduler Block Occupation Table (see page
223)
00111 MGT: Merge Group Table (see page 230)
01010 AVT: VBR Table (see page 280)
10000
QPT1 Upstream:
Queue Parameter Table 1 Up (see page 247)
Data Sheet
307
2001-12-17