PXF4333 Datasheet, PDF (294/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 98 EXTRAMC
External RAM Test Command Register
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
EXTRAMA0 E0_H
Written and Read by CPU
Bit
15
14
13
12
11
10
9
8
Unused(13:2)
Bit
7
6
5
4
3
2
1
0
Unused(1:0) CSRDW CSRDR CSRUW CSRUR CPRW CPRR
Setting a command bit starts the Read or Write procedure from/to the selected external
RAM. The corresponding bit is automatically cleared after completion of the Read/Write
procedure.
The address to be read or to be written is provided in registers EXTRAMA0 and
EXTRAMA1. The 32-bit wide data is transferred via registers EXTRAMD0 and
EXTRAMD1.
Note: Access to external RAM is only allowed before first cell flow.
CSRDW
Cell Storage RAM downstream write
CSRDR
Cell Storage RAM downstream read
CSRUW
Cell Storage RAM upstream write
CSRUR
Cell Storage RAM upstream read
CPRW
Cell Pointer RAM write
CPRR
Cell Pointer RAM read
Data Sheet
294
2001-12-17