PXF4333 Datasheet, PDF (288/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

BYPASS1
PU1
RES1
M1(3:0)
N1(5:0)
ABM-3G
PXF 4333 V1.1
Register Description
0
Division Factor 1 disabled.
1
Division Factor 1 enabled.
DPLL1 Bypass
Switching between bypass and non-bypass mode is glitch-free with
respect to the internal clock output. The DPLL1 is bypassed after
power-on reset and can be switched to non-bypass mode by
software during device configuration.
0
DPLL1 is internally bypassed,
i.e. DPLL1 clock input connected to DPLL1 clock output
1
DPLL1 is not bypassed,
i.e. DPLL1 clock output is generated by DPLL1
depending on its parameter configuration
Power Up DPLL1
0
DPLL1 is in power-down mode.
(The analog part of DPLL1 is switched-off for power
saving.)
1
DPLL1 is in power on (operational) mode.
Reset DPLL1
0
DPLL1 is in operational mode.
1
DPLL1 is in reset mode.
Note: The result of reset mode is identical to bypass
mode, but switching between reset and non-reset
status is not glitch-free with respect to the internal
clock output.
M1 Parameter of DPLL1
This parameter determines the first stage division factor of DPLL1.
The effective division factor is (M1 + 1) in the range 1..16.
N1 Parameter of DPLL1
This parameter determines the second stage multiplication factor of
DPLL1. The effective multiplication factor is (N1 + 1) in the range
1..64.
Data Sheet
288
2001-12-17