PXF4333 Datasheet, PDF (306/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 106 IMRC
Interrupt Mask Register Common
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
IMRC
E8_H
Written by CPU to control interrupt signal effective
events
Bit
15
14
13
12
11
10
9
8
IMRC(15:8)
Bit
7
6
5
4
3
2
1
0
IMRC(7:0)
IMRC(15:0)
Interrupt Mask Common
Each bit controls whether the corresponding interrupt indication in
register ISRC (same bit location) activates the interrupt signal:
1
Interrupt indication masked.
The interrupt signal is not activated upon this event.
0
Interrupt indication unmasked.
The interrupt signal is activated upon this event.
Data Sheet
306
2001-12-17