PXF4333 Datasheet, PDF (248/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Register Description
The queue number representing the table entry which needs to be read or written must
be written to the Word Address Register (WAR). The dedicated QPT1 table entry is read
into the xQPT1T0/xQPT1T1 transfer registers (x=U,D) or modified by the xQPT1T0/
xQPT1T1 transfer register values with a write mechanism. The associated mask
registers xQPTM0 and xQPTM1 allow a bit-wise Write operation (0 - unmasked, 1 -
masked). In case of Read operation, the dedicated xQPT1T0/xQPT1T1 register bit will
be overwritten by the respective QPT1 table entry bit value. In case of Write operation,
the dedicated xQPT1T0/xQPT1T1 register bit will modify the respective QPT1 table
entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to
select the QPT table bit field MAR(4:0) must be set to:
10_H for QPT1 upstream table,
18_H for QPT1 downstream table.
Bit 5 of MAR starts the transfer and is cleared automatically after execution.
Table 7-16 WAR Register Mapping for QPT Table Access
Bit
15
14
13
12
11
10
9
8
Unused(2:0)
QueueSel(12:8)
Bit
7
6
5
4
3
2
1
0
QueueSel(7:0)
QueueSel(12:0) Selects one of the 8192 queue parameter table entries.
Data Sheet
248
2001-12-17