PXF4333 Datasheet, PDF (53/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Functional Description
3.2.5.2 DPLL Programming
The DPLL features two factors programmed by parameters m and n in register
“PLL1CONF” on Page 287 :
f₁ = f_in ⁄ (m + 1)
;
f₂
=
f_in
×
-ⁿ-----+-----¹---
m+1
Register PLL1CONF
15
Lockedi Div2Eni Div1Eni Bypassi PUi RESi
Mi(3:0)
0
Ni(5:0)
f_in
(1)
1
f₁
2..15 MHz
f₂
(1)
(1)
X
(n + 1)
X
1/2 X
1/2
(m + 1)
(0)
(0)
(0)
f_out
Figure 3-8 DPLL Structure
The division factor determined by m must be chosen such that intermediate frequency
f₁ is in the range 2..15 MHz based on the input frequency at signal ‘SYSCLK’.
The multiplication factor determined by n must be chosen such that intermediate
frequency f₂ is twice or four times the final value in case of DPLL1.
Finally, one or two divisions by the two factors (f₁,f₂) may be enabled in case of DPLL1
to achieve the final clock frequency.
When choosing the factors m and n, two conditions must be met:
• n=1..24: f₁ must be in a range of 5..15 MHz
n=25..63: f₁ must be in a range of 2..6 MHz
• f₂ must be in a range of 100 to 200 MHz
3.2.5.3 Programming Example
The following numbers are assumed for this example:
• ABM-3G internal core clock: 52 MHz
Data Sheet
53
2001-12-17