PXF4333 Datasheet, PDF (268/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Register Description
The Read or Write process is controlled by the MAR (Memory Address Register). The 5
LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to
select the SCTF Upstream table, bit field MAR(4:0) must be set to 17_H and 1F_H for the
SCTF Downstream table respectively. Bit 5 of MAR starts the transfer and is
automatically cleared after execution.
Table 7-24 WAR Register Mapping for SCTFU/SCTFD Table access
Bit
15
14
13
12
11
10
9
8
Unused(9:2)
Bit
7
6
5
4
3
2
1
0
unused
SchedSel(6:0)
SchedSel(6:0) Selects one of the 128 core specific Scheduler Blocks.
Data Sheet
268
2001-12-17