HY5FS123235AFCP Datasheet, PDF (71/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Mirror Function
The GDDR4 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all
address lines assisting in routing devices back to back. The MF ball will affect RAS#, CAS#, WE#, CS# ,CKE#, A0, A1,
A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, BA0, BA1 AND BA2 and only detects a DC input. The MF ball should be
tied directly to VSS or VDD depending on the control line orientation desired.
Table 27 illustrates the pin location in relation to the polarity of the MF pin. The MF pin does not transition under
normal operation. MF can only transition when either the RESET or SEN pin are asserted.
Table 28 Mirror Function Signal Mapping
PIN
RAS#
CAS#
WE#
CS#
CKE#
A0/A10
A1/BA0
A2/A12
A3/A11
A4/A8
A5/BA1
A6/BA2
A7/A9
MF LOGIC STATE
LOW
HIGH
H2
H11
G4
G9
H10
H3
G9
G4
H3
H10
K2
K11
H4
H9
K3
K10
L4
L9
K11
K2
H9
H4
K10
K3
L9
L4
Rev. 1.2 /June. 2008
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