HY5FS123235AFCP Datasheet, PDF (70/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Table 27 Ballout Description
FBGA BALL-OUT
L3, M(2, 3) N2, R(2, 3), T(2,3)
D(3, 10), P(3, 10)
SYMBOL
DQ24-31
RDQS(0-3)
D(2, 11), P(2, 11)
WDQS(0-3)
J2
A(1, 12), C(1, 4, 9, 12), (E1, 4,
9, 12), H(1,9), N(1, 4, 9, 12),
R(1, 4, 9, 12), U(1, 12)
B(1, 4, 9, 12), D(1, 4, 9, 12),
F(4,9), G(2, 11), L(2, 11),
M(4,9), P(1, 4, 9, 12),
T(1, 4, 9, 12)
A(2, 11), F(1, 12), K(1, 12)
M(1, 12), U(2,11)
A(3, 10), G(1, 12), J(1, 12),
K(4, 9), L(1,12), U(3,10)
J(4, 9)
J3
A9
H11
RFU
VddQ
VssQ
Vdd
Vss
Vref
PERR#
MF
RFM
A4
ZQ
U4
SEN
U9
RESET
TYPE
I/O
Output
Input
Supply
Supply
Supply
Supply
Supply
Output
Reference
Reference
Input
Input
DESCRIPTION
Data Input/Output
READ Data Strobe: Output with read data. RDQS is edge-aligned
with read data. RDQS is used as the flag for WRITE DBI.
WRITE Data strobe: Input with write data.
WDQS is center-aligned to the input data.
Reserved for Future Use
DQ Power Supply: +1.5V
‚ 0.045V or +1.8V
‚ 0.09V or
+2.0V ‚ 0.1V. Isolated on the die for improved noise immunity.
DQ Ground: Isolated on the die for improved noise immunity.
Power Supply: +1.5V ‚ 0.045V or +1.8V ‚ 0.09V or
+2.0V ‚ 0.1V
Ground.
Reference Voltage.
Parity error
Mirror Function for clamshell mounting of DRAMs
When the MF ball is tied LOW, RFM receiver is disabled and it
recommended to be driven to a static LOW state. However, either
static HIGH or floating state on this pin will not cause any
problem for the GDDR4 SGRAM.When the MF ball is tied HIGH,
RAS(H2) becomes RFM due to mirror function and the receiver is
disabled. It is recommended to be driven to a static LOW state.
However, either static HIGH or floating state on this pinwill not
cause any problem. for the GDDR4 SGRAM
External Reference Pin for autocalibration
Scan enable. Must tie to the ground when not in use.
Reset Pin. The RESET pin is a VDDQ CMOS input.
Rev. 1.2 /June. 2008
70