HY5FS123235AFCP Datasheet, PDF (10/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Burst Length
Read and write accesses to the GDDR4 SDRAM are burst-oriented, with the burst length fixed at 8 and thus not
programmable in the MRS as with many other DRAMs. The burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A3–Ai (where Ai is the most significant column address bit for a given
configuration) as the GDDR4 SDRAM has a fixed burst length of 8. Also GDDR4 SDRAM has a fixed start address of 000
within the block, thus A2-A0 does not select the access order within a burst and must be set to zero.
Table 2
Burst Order
Burst Length
8
Starting Column Address
A2 A1 A0
000
Order of Access within a burst
Type = Sequential
0-1-2-3-4-5-6-7
CAS Latency
The READ latency, or CAS latency, is the delay between the registration of a READ command and the availability of the
first piece of output data. The latency is set using bits A3-A6 and values of 7 - 20 are supported in the specification.
Vendor specifications should be checked for value(s) of CAS latency supported.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
coincident with clock edge n + m.
Speed
-06
-07
-08
-09
CL 22
<=1.6
(RDBI)
CL 21
Table 3
Cas Latency
Allowable Operating Frequency (GHz)
CL20
CL19
CL18
CL17
CL16
<=1.6
<=1.4
(RDBI)
<=1.2
(RDBI)
<=1.4
<=1.2
<=1.1
(RDBI)
CL 15
<=1.1
CL 14
Rev. 1.2 /June. 2008
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