HY5FS123235AFCP Datasheet, PDF (33/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Notes
1. This table applies when CKE#n1 was LOW and CKE#n is LOW (see Table 8) and after t_XSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands
shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and t_RP has been met.
Row Active: A row in the bank has been activated, and t_RCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled.
Write: A WRITE burst has been initiated, with auto precharge disabled.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Table 9, and according to
Table 10.
Precharging: Starts with registration of a PRECHARGE command and ends when t_RP is met.
Once t_RP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when t_RCD is met.
Once t_RCD is met, the bank will be in the row active state.
Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and
ends when t_RP has been met. Once t_RP is met, the bank will be in the idle state.
Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and
ends when t_RP has been met. Once t_RP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command;
COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when t_RC is met.
Once t_RC is met, the GDDR4 SDRAM will be in the all banks idle state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when t_MRD has
been met. Once t_MRD is met, the GDDR4 SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t_RP is met.
Once t_RP is met, all banks will be in the idle state.
READ or WRITE: Starts with the registration of the ACTIVE command and ends the last valid data nibble.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for
precharging.
9. Reads or Writes listed in the Command/Action column include Reads or Writes with auto precharge enabled and
Reads or Writes with auto precharge disabled.
10. Requires appropriate DM masking.
11. A WRITE command may be applied after the completion of the READ burst
Rev. 1.2 /June. 2008
33