HY5FS123235AFCP Datasheet, PDF (28/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
PRECHARGE
The PRECHARGE command (see Figure 19) is used to deactivate the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent row access a specified time (t_RP) after the PRECHARGE
command is issued.
Input A8 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged,
inputs BA0-BA2 select the bank. Otherwise BA0-BA2 are treated as “Dont Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command
being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the
previously open row is already in the process of precharging.
P rech arg e
CK#
CK
CKE# LO W
CS#
RAS#
CAS#
W E#
A 9-A 12
A 0 ,A 2 ,A 3 ,A 7
EN AP
A8
D IS A P
B A 0 -B A 2
A 1 ,A 5 ,A 6
BA
B A = B a n k A d d re s s ( if A 8 is L O W ;
O th e rw is e t D o n st C a re u )
Figure 19: PRECHARGE command
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but
without requiring an explicit command. This is accomplished by using A8 (A8 = High), to enable Auto Precharge in
conjunction with a specific READ or WRITE command.
A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon
completion of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each
individual READ or WRITE command.
Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharing time (t_RP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation
section of this specification.
AUTO REFRESH
AUTO REFRESH command (see Figure 20) is used during normal operation of the GDDR4 SDRAM. This command is
non persistent, so it must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. The GDDR4 SDRAM requires AUTO REFRESH
commands at an average periodic interval of t_REFI. The values of t_REFI for different densities are listed in Table 4.
Rev. 1.2 /June. 2008
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