HY5FS123235AFCP Datasheet, PDF (21/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
READ
READ burst is initiated with a READ command. as shown in Figure 11. The starting column and bank addresses are
provided at the READ command and the following clock cycle, and auto precharge is either enabled or disabled for that
access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the completion of the
burst after t_RAS min has been met or after the number of clock cycles programmed in EMR3 for RAS depending on the
implementation choice per DRAM vendor.
During READ bursts, the first valid data-out element from the starting column address will be available following the
CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive
RDQS edge. The GDDR4 SDRAM drives the output data edge aligned to RDQS. And all outputs, i.e. DQs and RDQS, are
also edge aligned to the clock. Prior to the first valid RDQS rising edge, a cycle is driven and specified as the READ pre-
amble. The single preamble consists of a half cycle High followed by a half cycle of Low driven by the GDDR4 SDRAM.
For the multi-cycle preamble it should be set in extended mode register. The cycle on RDQS consisting of a half cycle
Low coincident with the last data-out element followed by a half cycle High is known as the read postamble, and it will
be driven by the SDRAM. The SDRAM toggles RDQS only when it is driving valid data on the bus.
Upon completion of a burst, assuming no other command has been initiated; the DQs and RDQS will be in a Hi-Z state.
Data from any READ burst may be concatenated with data from a subsequent READ command. A continuous flow of
data can be maintained. The first data element from the new burst follows the last element of a completed burst.
The new READ command should be issued at least 4 cycles after the first READ command. A PRECHARGE can also be
issued to the SDRAM with the same timing restriction as the new READ command if t_RAS is met. A WRITE can be
issued any time after a READ command as long as the bus turn around time is met. READ data cannot be truncated.
The data inversion flag is driven on the DM signal to identify whether the data is true or inverted data. If DM is HIGH,
the data will is inverted and not inverted when it recognizes DM is LOW. READ Data Inversion can be programmed as
a Disable (A8=0) or Enable (A8=1) in the EMRS.
Rev. 1.2 /June. 2008
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