HY5FS123235AFCP Datasheet, PDF (55/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Table 19 Clock Input Operating Conditions
Parameter
Clock Input Mid-Point
Voltage; CK and CK#
Clock Input Differential
Voltage; CK and CK#
Clock Input Differential
Voltage; CK and CK#
Clock Input Voltage Level;
CK and CK#
Clock Input Crossing Point
Voltage; CK and CK#
Symbol
VMP (DC)
VID (DC)
VID (AC)
VIN
VIX (AC)
Min
1.16
0.22
0.5
0.42
VREF - 0.15
POD18
Typ
-
-
-
-
VDDQ*0.70
Max
1.36
Unit Note
V
1, 2
VDDQ
V
1, 3
VDDQ + 0.5
V
3
VDDQ + 0.3
V
VDDQ + 0.15 V
2
Notes :
1. For AC operations, all DC clock requirements must be satisfied as well.
2. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the
DC level of the same.
3. VID is the magnitude of the difference between the input level in CK and the input level on CK#. The input reference
level for signals other than CK and CK# is VREF.
4. The CK and CK# input reference level (for timing referenced to CK and CK#) is the point at which CK and CK# cross.
5. CK and CK# input slew rate must be greater than 3V/ns for VDDQ=1.8V(typ)
Maximum Clock Level
CK
VMP(DC) VIX(AC) VID(DC) VID(AC)
CK#
Minimum Clock Level
Figure 38: Clock Input Waveform
Rev. 1.2 /June. 2008
55