HY5FS123235AFCP Datasheet, PDF(46/74 Page) Hynix Semiconductor

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HY5FS123235AFCP Datasheet, PDF (46/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

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HY5FS123235AFCP

Changing Clock Frequency

( Not only frequency but also VDD change sequence as below.)

Clock Frequency Change Sequence - AREF commands

Step 1) Wait until all commands have finished, all banks are idle.

Step 2) Only NOP or DESELECT or AREF commands may be issued (must meet setup/hold relative to clock while clock

is changing) to GDDR4 SDRAM for the entire sequence unless stated to do otherwise. AREF commands must fulfill

AREF burst requirements.

Step 3) If new clock period is between the range of tCK (Max DLL Off) to tCK (Min DLL Off), then turn DLL off via EMRS

Step 4) Change the clock frequency and wait until clock is stabilized.

Step 5) If new clock period is smaller than tCK(Max DLL On), then turn DLL on via EMRS register write.

Step 6) Self Ref. Insert

Step 7) If the DLL is enabled, then complete steps 6a and 6b:

7a) Reset the DLL by writing to the MRS register.

7b) Wait tDL clock cycles before issuing any commands to the GDDR4 SDRAM.

Step 8) GDDR4 SDRAM is ready for normal operation.

Clock Frequency Change Sequence - NOP/DESELECT commands

Step 1) Wait until all commands have finished, all banks are idle.

Step 2) Send NOP or DESELECT (must meet setup/hold relative to clock while clock is changing) to GDDR4 SGRAM for

the entire sequence unless stated to do otherwise. The user must take are of AREF requirements.

Step 3) If new clock period is between the range of tCK(Max DLL Off) to tCK (Min DLL Off), then turn DLL off via EMRS