HY5FS123235AFCP Datasheet, PDF (15/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
EXTENDED MODE REGISTER 2 (EMR2)
The Extended Mode Register 2 controls functions beyond those controlled by the Mode Register and Extended Mode
Register; these additional functions include the offset for both the driver and termination as shown in Figure 5. The
Extended Mode Register 2 is programmed via the MODE REGISTER SET (MRS) command (with BA0=0, BA0=1 and
BA2=0) and will retain the stored information until it is reprogrammed or the device loses power. The Extended Mode
Register 2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the spec-
ified time t_MRD before initiating any subsequent operation. Violating either of these requirements will result in unspec-
ified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may
result. RFU bits are reserved for future use and must be programmed to 0.
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
0
RFU
OCD-Termination
/Pull-Up-offset
OCD-PullDown
Driver offset
A5
A4
A3
OCD-Termination
/Pull-Up-offset
000
0
001
1
010
2
011
3
100
-4
101
-3
110
-2
111
-1
A2 A1 A0
000
001
010
011
100
101
110
111
OCD-PullDown
Driver offset
0
1
2
3
-4
-3
-2
-1
Figure 5: Extended Mode Register 2 Definition
OCD PullDown Driver and Termination PullUp Driver offset
GDDR4 SDRAM adds the ability to add or subtract offsets from both the Driver and Terminator. See section entitled
DRIVER & TERMINATION for more details.
Rev. 1.2 /June. 2008
15