HY5FS123235AFCP Datasheet, PDF (61/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
26. This limit is actually a nominal value and does not result in a fail value. CKE# is LOW during REFRESH command period
(t_RFC [MIN]) else CKE# is HIGH (e.g., during standby).
27. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in
order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge, and the drive
should achieve the same slew rate through the AC values.
28. The input capacitance per pin group will not differ by more than this maximum amount for any given device.
29. CK and CK# input slew rate must be >= 3 V/ns.
30. DQ and DM input slew rates must not deviate from WDQS by more than 10 percent. If the DQ/DM/WDQS slew rate is less than
3 V/ns, timing is no longer referenced to the midpoint but to the Vil(AC) maximum and Vih(AC) minimum points.
31. The clock is allowed up to ‚ 90ps of jitter. Each timing parameter is allowed to vary by the same amount.
32. t_HP (MIN) is the lesser of t_DQSL minimum and t_DQSH minimum actually applied to the device CK and CK# inputs, collectively
during bank active.
33. For READs and WRITEs with auto precharge the GDDR4 device will hold off the internal PRECHARGE command until t_RAS (MIN)
has been satisfied.
34. The last rising edge of WDQS after the write postamble must be driven high by the controller. WDQS cannot be pulled high by
the on-die termination alone. For the read postamble the GDDR4 will drive the last rising edge of the read postamble.
35. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
36. Vih overshoot: Vih (MAX) = VddQ + 0.5V for a pulse width <= 500ps and the pulse width cannot be greater than 1/3 of
the cycle rate. Vil undershoot: Vil (MIN) = 0.0V for a pulse width <= 500ps and the pulse width cannot be greater than 1/3 of
the cycle rate.
37. The DLL must be reset when changing the frequency, follFowed by t_DL.
38. The tIPW parameter defines the min pulse width for command/address. This is used to tell the input receiver designer the
max bandwidth to design to.
39. When read to read command is entered in Rank=2, the tCCD is 6clocks. And other cases are all 4 clocks.
Rev. 1.2 /June. 2008
61