HY5FS123235AFCP Datasheet, PDF (65/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
POD I/O SYSTEM
The POD I/O system is optimized for small systems with data rates exceeding 2.0 Gbps. The system allows a single
Master device to control one, two or four slave devices. The POD driver uses a 40 Ohm output impedance that drives
into a 60 Ohm equivalent terminator tied to VDDQ. Single, dual and quad load systems are shown as follows:
VDDQ
40 Ohm
Data Bit
VDDQ
240 Ohm
240 Ohm
240 Ohm
240 Ohm
4 Slaves
40 Ohm
Data Bit
VDDQ
120 Ohm
120 Ohm
2 Slaves
40 Ohm
Data Bit
60 Ohm
1 Slave
Figure 39: System Configurations
The POD Master I/O cell is comprised of a 40 Ohm driver and terminator of 60 Ohms. The Master POD cell’s terminator
is disabled when the output driver is enabled. The basic cell is shown in Figure 40.
VDDQ
60 Ohm Terminator
Enabled when receiving
Output Data
Output Enable
DQ
Rev. 1.2 /June. 2008
VSSQ
60 Ohm pull-up and 40 Ohm pull-down
when transmitting
Figure 40: Master I/O Cell
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