HY5FS123235AFCP Datasheet, PDF (51/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
LPTERM
As GDDR4 SDRAM gains adoption in mobile applications there is a desire from users to support a mode where
terminations can be disabled on the memory for the majority of the signals while maintaining termination on the
strobes for proper clocking of the interface. The intent is the GDDR4 SDRAM would be operated at a slower condition
possibly with the DLL disabled while still meeting the AC timings of the DRAM.
This feature is available during normal operation but requires the memory controller meet the device specifications by
operating at a reduced frequency. Absolute frequencies supported by the GDDR4 SDRAM are vendor specific. Control
of the Low power mode is accomplished through the mode register field defined in Table 13. The Low Power
Termination mode can only be enabled when DQ termination is enabled in the ZQ/2 or ZQ/4 mode.
Table 14 Low Power Termination Control
LPTERM
0
Disabled
1
Enabled
Table 14 defines the termination states for the each signal group. The value EMRS[Termination] is meant to reference
the value defined in the EMRS register for the state of ODT termination for actual termination impedance.
Table 15 Termination Support
Signal Group
LPTERM Disabled LPTERM Enabled
CLK, CLK#
N/A
N/A
Address
Enabled
Disabled
RAS#, CAS#, WE#,CS#
Enabled
Disabled
CKE#
Enabled
Disabled
RDQS[3:0]
EMRS[Termination]
Disabled
WDQS[3:0]
EMRS[Termination] EMRS[Termination]
DQ[31:0], DM[3:0] EMRS[Termination]
Disabled
Rev. 1.2 /June. 2008
51