HY5FS123235AFCP Datasheet, PDF (31/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Power-Down
GDDR4 SDRAMs require CKE# to be active at all times that an access is in progress: from the issuing of a READ or
WRITE command until completion of the burst. For READs, a burst completion is defined when the Read Postamble
is satisfied; For WRITEs, a burst completion is defined when the write postamble is satisfied.
Figure 23 shows Powerdown entry and exit. Powerdown is entered when CKE# is registered HIGH. If powerdown
occurs when all banks are idle, this mode is referred to as precharge powerdown; if power-down occurs when there
is a row active in any banks, this mode is referred to as active powerdown. Entering power-down deactivates the
input and output buffers, excluding CK, CK#, RESET and CKE#. However, powerdown duration is limited by the
refresh requirements of the device. While in powerdown, CKE# and RESET must be HIGH and a stable clock signal m
ust be maintained at the inputs of the GDDR4 SDRAM, while all other input signals are “Don’t Care”.
The power-down state is synchronously exited when CKE# is registered LOW (in conjunction with a NOP or
DESELECT command). A valid executable command may be applied t_PDEX cycles later.
T0
T1
T2
T3
T4
CK#
CK
CKE#
t_IS
t_RP
CMD NOP
VALID
No READ/WRITE
Access in progress
NOP
Enter
Power Down
Mode
NOP
t_CKE
NOP
Tm Tm+1 Tm+2 Tn
t_IS
t_PDEX
NOP
Exit
Power Down
Mode
NOP
VALID
Figure 23: Power-Down Entry and Exit
Note:
1. Minimum CKE# pulse width must satisfy t_CKE.
2. After issuing Power Down command, two more NOPs should be issued.
Rev. 1.2 /June. 2008
31