HY5FS123235AFCP Datasheet, PDF (49/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
DRIVER & TERMINATION
Programmable Impedance Output Buffer and Active Terminator
GDDR4 SDRAM use a programmable impedance output buffer. This enables a user to match the driver impedance to
the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ pin and Vss.
The value of the resistor must be six times the desired driver impedance. For example, a 240ohm resistor is required
for an output impedance of 40ohm. To ensure that output impedance is one-sixth the value of RQ (within 10 percent),
the range of RQ is 210ohm to 270ohm (35ohm45ohm output impedance). RESET, CK and CK# are not internally
terminated. CK and CK# need to be terminated on the system using external one percent resistors to Vdd.
The output impedance is updated during all AUTO REFRESH commands to compensate for variations in supply
voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not
affect device operation, and all data sheet timing and current specifications are met during an update.
The device will power up with an output impedance set to nominal, close to 40ohm. To guarantee optimum output
driver impedance after power-up, the GDDR4 SDRAM needs 350 clock cycles after the clock is applied and stable to
calibrate the impedance. The user can operate the part with fewer than 350 clock cycles, but optimal output imped-
ance is not guaranteed.
The value of RQ is also used to calibrate the internal address/command termination resistors. The termination values
are selectable at power up using CKE# and A0 with values of 60, 120 and 240ohm supported. The value of RQ is used
to calibrate the internal DQ termination resistors. The two termination values that are selectable are 1/4 of RQ and
1/2 of RQ.
Impedance Control
GDDR4 SDRAM output driver impedance and termination impedance is programmable through EMRS. The offset
impedance step values may be non-linear and will vary across suppliers and across the yield distribution and across
temperature. The offsets are only applied to the DQ, DQM, RDQS and WDQS signals. No programmability is provided
for the address and command signals. With negative offset steps the Driver Strength will be decreased and the Ron
will be increased. With positive offset steps the Driver Strength will be increased and Ron will be decreased.
With negative offset steps the Termination value will be increased. With positive offset steps the Termination value will
be decreased. The Termination offset steps will be also applied to the Pullup Driver Strength settings. IV curves and AC
timings are only guaranteed with zero offset.
Auto-calibreaded/nominal
OCD impedance
EMRS2 controlled OCD
impedance offset
Auto-calibreaded ODTl
Pull-up impedance
EMRS2 controlled ODT
impedance offset
OCD pull-down impedance
Figure 35: Off sets
ODT pull-up impedance
Rev. 1.2 /June. 2008
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