HY5FS123235AFCP Datasheet, PDF (11/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
WRITE Latency
The WRITE latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability
of the first bit of input data. The latency can be set from 1 to 7 clocks depending on the operating frequency and desired
current draw. When the write latencies are set to small values (1,2,... clocks), the input receivers never turn off, in turn,
raising the operating power. When the WRITE latency is set to higher values (... 6, 7 clocks) the input receivers turn on
when the WRITE command is registered. Vendor specifications should be checked for value(s) of WL supported and the
specific value(s) of WL where the input receivers are always on or only turn on when the WRITE command is
registered.
If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
coincident with clock edge n + m.
WRITE Recovery (WR)
WR must be programmed into bits A0-A2 with a value greater than or equal to RU {tWR/tCK}, where RU stands for
round up, tWR is the analog value from the vendor datasheet and tCK is the operating clock cycle time. the WR regis-
ter bits are not a required function and may be implemented at the discretion of the memory manufacturer.
Test Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits
A0-A6 and A8-A12 set to the desired values. Test Mode is initiated by issuing a MODE REGISTER SET command with
bits A7 set to one, and bits A0-A7 and A9-A12 set to the desired values. Test mode functions are specific to each DRAM
vendor and their exact function are hidden from the user.
DLL Reset
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A8 set to zero, and bits
A0-A7 and A9-A12 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with
bit A8 set to one, and bits A0-A7 and A9-A12 set to the desired values. When a DLL Reset is complete the GDDR4 SDRAM
Reset bit, A8 of the mode register is self clearing (i.e. automatically set to a zero by the GDDR4 SDRAM).
Rev. 1.2 /June. 2008
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