HY5FS123235AFCP Datasheet, PDF (27/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
T0
CK#
CK
WDQS
DQ
Figure 17: WRITE Capture
T1 T1n T2 T2n T3 T3n T4 T4n T5
t_DQSL t_DQSH
DIn
DI
n+7
DM
t_DS
t_DH
Show n for WPRE=1 tCK
DONsT CARE TRANSITIONING DATA
T0
CK#
CK
COMMAND WRITE
ADDRESS
Bank a,
Col b
T1
NOP
Col b
Figure 18: WRITE to READ
T2
T3 T3n T6 T6n T7
T8
T12
T13
NOP
NOP
NOP
NOP
NOP
tWTR = 5
READ
Bank a,
Col n
NOP
Col n
T24 T24n T25 T25n
NOP
NOP
t_DQSS(NOM)
WDQS
t_DQSS
DQ
DM
RDQS
DQ ODT ODT Enabled
RDQS ODT ODT Enabled
Snoop ODT ODT Enabled
t_WPRE
DIb
DBI
t_WPST
DI
b+7
DBI
b+7
CL = 13
DOn
DBI
ODT Off
ODT Off
ODT Off
DONsT CARE TRANSITIONING DATA
1. DI b = data-in for column b.
2. Seven subsequent elements of data-in are applied in the specified order following DI b.
3. t_WTR is referenced from the first positive CK edge after the last written data.
4. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to
different devices, in which case t_WTR is not required and the READ command could be applied earlier.
5. A8 is LOW with the WRITE command (auto precharge is disabled).
6. WRITE latency is set to 3.
7. The 8n prefetch architecture requires a 5-clock WRITE to READ turnaround time (t_WTR).
Rev. 1.2 /June. 2008
27