HY5FS123235AFCP Datasheet, PDF (16/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
EXTENDED MODE REGISTER 3 (EMR)
The Extended Mode Register 3 controls functions beyond those controlled by the Mode Register, Extended Mode
Register and Extended Mode Register 2; these additional functions include LPTERM and Parity as shown in Figure 6.
The Extended Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command (with BA0=1, BA1=1
and BA2=0) and will retain the stored information until it is reprogrammed or the device loses power. The Extended
Mode Register 3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait
the specified time t_MRD before initiating any subsequent operation. Violating either of these requirements will result in
unspecified operation.
If the user activates bits in the Extended Mode Register 3 in an optional field, either the optional field is activated (if
option is implemented in the device) or no action is taken by the device ( if option is not implemented). Reserved
states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are
reserved for future use and must be programmed to 0.
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
1 RFU
DRAM Info
LP
TERM
RFU
A7
A6
DRAM Info
A5 LPTERM
0
0
Vendor ID
0 Disabled
0
1 PERR_Info/optional
1 Enabled
1
0
Vendor Specific
1
1
Vendor Specific
Figure 6: Extended Mode Register 3 Definition
LPTERM
GDDR4 SDRAM adds a low power mode which reduces power consumed for I/O termination by disabling the
termination for a subset of the pins. See Section entitled DRIVER & TERMINATION for more details.
DRAM Info
DRAM info is used to select either Parity info or Vendor ID info to be output.
Rev. 1.2 /June. 2008
16