HY5FS123235AFCP Datasheet, PDF (60/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Note
1. All voltages referenced to VSS.
2. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage and temperature range specified.
3. Outputs measured with equivalent load (vendor specific) terminated with 60ohms to VDDQ.
4. All parameters assume proper device initialization.
5. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC operating conditions.
6. AC timing and Idd tests may use a Vil-to-Vih swing of up to 1.0V in the test environment, but input timing is still referenced to
Vref (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the device is 3 V/ns in the range between Vil(AC)
and Vih(AC).
7. The AC and DC input level specifications are a pseudo open drain design for improved high-speed signaling.
8. Vref is expected to equal 70 percent of VddQ for the transmitting device and to track variations in the DC level of the same.
Peak-to-peak noise on Vref may not exceed ‚ 2 percent of the DC value. Thus, from 70% of VddQ, Vref is allowed ‚ 25mV for



DC
error and an additional ‚ 25mV for AC noise.
9. GDDR4 SDRAMs are required to support a minimum clock frequency of 400MHz for normal DLL-on operation, regardless of the
speed bin of the device.
10. If users need operation below 400MHz, they should use the DLL-off mode of the device.
11. Vid is the magnitude of the difference between the input level on CK and the input level on CK#.
12. The value of Vix is expected to equal 70 percent of VddQ for the transmitting device and must track variations in the DC level of
the same.
13. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at minimum CAS
latency and does not include the on-die termination current. Outputs are open during Idd measurements.
14. Enables on-chip refresh and address counters.
15. Idd specifications are tested after the device is properly initialized.
16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference
level for signals other than CK/CK# is Vref.
17. Command/Address input slew rate = 3 V/ns. If the slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint
but to the Vil(AC) maximum and Vih(AC) minimum points.
18. Inputs are not recognized as valid until Vref stabilizes. Exception: during the period before Vref stabilizes, MF, CKE# <= 0.3 x
VddQ is recognized as LOW.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
20. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
21. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus
turnaround.
22. It is recommended that WDQS be valid (HIGH or LOW) on or before the WRITE command.
23. MIN (t_RC or t_RFC) for Idd measurements is the smallest multiple of t_CK that meets the minimum absolute value for the respective
parameter. t_RAS (MAX) for Idd measurements is the largest multiple of t_CK that meets the maximum absolute value for t_RAS.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device.
25. Referenced to each output group: RDQS0 with DQ0–DQ7, RDQS1 with DQ8–DQ15, RDQS2 with DQ16–DQ23, and RDQS with
DQ24–DQ31.
Rev. 1.2 /June. 2008
60