HY5FS123235AFCP Datasheet, PDF (35/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Table 11 Minimum Delay Between Commands to Different Banks with Auto
Precharge Enabled
From Command
To Command
WRITE
with AUTO
PRECHARGE
READ
with AUTO
PRECHARGE
READ or READ with AUTO PRECHARGE
WRITE or WRITE with AUTO PRECHARGE
PRECHARGE
ACTIVE
READ or READ with AUTO PRECHARGE
WRITE or WRITE with AUTO PRECHARGE
PRECHARGE
ACTIVE
Minimum delay
(with concurrent auto precharge)
[WL + (BL/2)] t_CK + t_WTR
(BL/2) t_CK
2 t_CK
2 t_CK
(BL/2) * t_CK
[CL+(BL/2) + 2 - WL] * t_CK
2 t_CK
2 t_CK
CL = CAS latency (CL) rounded up to the next integer
BL = Burst length
WL = WRITE latency
4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
7. Requires appropriate DM masking.
Rev. 1.2 /June. 2008
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