HY5FS123235AFCP Datasheet, PDF (6/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
INITIALIZATION
GDDR4 SDRAMs must be powered up and initialized in a predefined manner as shown in Figure 1.
Operational procedures other than those specified may result in undefined operation.
The Mode Register and Extended Mode Registers do not have default values except EMR[A3:A2] and EMR3[A5].
If they are not programmed during the initialization sequence, it may lead to unspecified operation.
1 Apply Power to VDD
2 Apply power to VDDQ at same time or after power is applied to VDD
3 Apply VREF at same time or after power is applied to VDDQ
4 After power is stable, provide stable clock signals
5 Assert and hold RESET low
6 Wait a minimum of 200us
Set CKE# and A0 to the desired address & command on die termination settings,
7 then bring RESET High to latch in the logic state of CKE# and A0. Must be met
during this procedure. See Table 1 for the values and logic states for CKE# and A0
8 Bring CKE# low after t_ATH is satisfied
9 Wait at least 200us referenced from the beginning of t_ATS
10 Issue at least 2 NOP commands
11 Issue a PRECHARGE ALL command followed by NOP commands until t_RP is satisfied
Issue MRS command to the mode register and the 3 extended mode registers in
12 _{any order. tMRD must be met during this procedure}
13 Issue two AUTO REFRESH commands
14 ^{After tRFC is satisfied from the second AUTO REFRESH command and tDL is}
satisfied, the device is ready for operation
Figure 1: GDDR4 Initialization Sequence
Rev. 1.2 /June. 2008
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