HY5FS123235AFCP Datasheet, PDF (36/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
READ and WRITE DBI
The GDDR4 Data Bus Inversion (DBI) logic reduces the AC power (DBIac) as shown in the flow chart in Figure 24a for
READs. The GDDR4 DBI logic reduces the AC power as shown in the flow chart in Figure 25a for WRITEs.
GDDR4 DBI logic reduces the DC power (DBIdc) as shown in the flow chart in Figure b for READs.
The GDDR4 DBI logic reduces the DC power as shown in the flow chart in Figure b for WRITEs.
The mapping of the DBI flag for READs and WRITEs are as follows:
Table 12 DBI Flag mapping for READ
Data
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DBI Flag
DM[0]
DM[1]
DM[2]
DM[3]
Table 13 DBI Flag mapping for WRITE
Data
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DBI Flag
RDQS[0]
RDQS[1]
RDQS[2]
RDQS[3]
Note:
When the DBI Flag equals 1 the Data is inverted,
The timing diagram in Figure a shows the READ timing of the DM and the read data DQ.
The timing diagram in Figure 26b shows the WRITE timing of the RDQS and the write data DQ.
Rev. 1.2 /June. 2008
36