HY5FS123235AFCP Datasheet, PDF (57/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Table 21 AC Timings
(Recommanded operating condition; 0°C <= TC <_-0=₆85°C)
-07
PARAMETER
SYMBOL
MIN MAX MIN MAX
-08
MIN MAX
-09
unit notes
MIN MAX
DQS output access time from CK/CK tDQSCK -0.14 +0.14 -0.16 +0.16 -0.19 +0.19 -0.20 +0.20 ns
Clock high-level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29
Clock low-level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29
CL=20 0.6 2.5
-
-
-
-
-
-
ns
9,
CL=18
Clock cycle time
tCK
CL=17
0.7 2.5
-
-
-
0.8 2.5
-
-
ns _10,
-
ns ^31,
CL=15
36
0.9
2.5 ns
Write Latency
tWL
2~7
-
2~7
-
2~7
-
2~7
- tCK
DQ and DM input setup time
tDS
0.11
0.12
0.12
0.13
ns 25, 30
DQ and DM input hold time
tDH
0.11
0.12
0.12
0.13
ns 25, 30
Active terminaton
setup time
tATS
9
9
9
10
ns
Active termination
Hold time
tATH
9
9
9
10
ns
WDQS input high-level width
tDQSH 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
WDQS input low-level width
tDQSL 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
RDQS - DQ skew
tDQSQ -0.10 0.10 -0.11 0.11 -0.11 0.11 -0.12 0.12 ns 25
Write command to 1st WDQS
latching transition
tDQSS
WL-0.2
WL+
0.2
WL-0.2
WL+
0.2
WL-0.2
WL+
0.2
WL-0.2
WL+
0.2
tCK
RDQS falling edge to CK setup time
tDSS 0.25
0.25
0.25
0.25
tCK
RDQS falling edge from CK hold time tDSH 0.25
0.25
0.25
0.25
tCK
Half strobe period
tHP
0.45
0.45
0.45
0.45
tCK 32
Jitter over 1~6 clock cycle error
tJ
-
0.03
-
0.03
-
0.03
-
0.03 tCK
DQ & RDQS high-impedance time
from CK/CK#
tHZ -0.18
-018
-0.2
-0.2
ns 19
DQ & RDQS low-impedance time
from CK/CK#
tLZ
-0.18
-018
-0.2
-0.2
ns 19
Address and control input setup time tIS
0.18
0.18
0.20
0.23
ns 17
Address and control input hold time
tIH
0.18
0.18
0.20
0.23
ns 17
Address and control input pulse width tIPW 0.40
0.40
0.50
0.55
ns 38
MODE REGISTER SET command
period
tMRD
4
4
4
4
tCK
DLL enable to READ command delay tDL
7K
7K
7K
7K
tCK
Rev. 1.2 /June. 2008
57