HY5FS123235AFCP Datasheet, PDF (42/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
DataTraining
GDDR4 includes a training scheme that uses normal WRITE and READ operations for data training. Before starting
data training, the GDDR4 SGRAM must be powered up and initialized in a predefined manner to prevent undefined
operations. READ data training is started by going through step 1~ step 8 sequentially. After the READ data training is
completed, the WRITE data training can be started or vice versa. The preferred manner is READ data training first and
then WRITE data training.tCKL is defined as the low speed clock frequency used to train READs and is specified by the
user. tSHFC is the Stable High Frequency Clock that has been trained.
READ Data Training Sequence
Step1: The GDDR4 SGRAM must be initialized properly and set to the low speed clock frequency.
Step2: Issue a WRITE command to load the data pattern at tCKL.
The Memory Contoller Logic defines the data pattern for the training.
During the WRITE, REFRESH commands can be used if required.
Step 3: After completing the WRITE at tCKL, the clock frequency is then changed to the target frequency.
A DLL reset is required after changing the frequency. The READ command must occur within 10ms to
prevent data loss in case there is no REFRESH command.
Step 4. The controller needs to select a DQ(or Byte) to be trained and set a minimum delay.
Step 5: Issue normal READ commands. During normal READ operation, REFRESH commands can be issued
if required.
Step 6: After the READ command is issued, if the step is not Max. then go to Step 5. Repeat Step 5 and Step 6 until
all of the delay steps are scanned.
Step 7. If all DQs(or Byte) are not checked, then go to Step 4. Repeat Step 4 to Step 7 until all the DQs are scanned.
Step 8. If all completed, then END of READ data training
Rev. 1.2 /June. 2008
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