HY5FS123235AFCP Datasheet, PDF (24/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
T0
CK#
CK
COMMAND READ
ADDRESS
Bank a,
Col n
T1
NOP
Col n
Figure 14: READ to WRITE
T13
T14 T14n T15 T15n T16 T16n T17 T17n T18
NOP
NOP
WRITE
NOP
NOP
NOP
Bank,
Col b
Col b
T19 T19n T20 T20n
NOP
NOP
CL = 14
RDQS
DBI
WDQS
t_WL=5
DQ
DM
DQ ODT ODT Enabled
DOn
DO
n+7
DBIn
DO
n+7
DQ ODT Disabled
DIb
ODT Enabled
RDQS ODT ODT Enabled
RDQS ODT Disabled
ODT Enabled
Snoop ODT ODT Enabled
DQ RDQS ODT Disabled
ODT Enabled
DONsT CARE TRANSITIONING DATA
Notes:
1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Data-in elements are applied following DI b in the programmed order.
5. Shown with nominal t_AC, and t_DQSQ.
6. t_DQSS in nominal case. RDQS will start driving HIGH one half-clock cycle prior to the first falling edge of RDQS.
READ and DLL Off Mode
The GDDR4 uses a DLL to synchronize the byte lane to the clock. Although the DLL provides accurate clocking of data
out, it requires a minimum operating frequency to function properly. The EXTENDED MODE REGISTER provides an
avenue to turn the DLL off for running at lower frequencies.
The GDDR4 devices default into the DLL off mode upon power-up. The device enters the DLL on mode of operation if
and when the DLL is enabled, via a MODE REGISTER SET Command to the Extended Mode Register. Once in the DLL
on mode, the device remains in that mode until powered down or turned off via the EXTENDED MODE REGISTER.
With the DLL off mode the output, DQ and DQS transitions may or may not align with CK and CK# transitions,
depending on clock frequency and CAS Latency settings.
The burst READ operation is a bit different from the standard DLL on mode. The time frame from the READ command
to first data out is defined by the CAS latency minus one plus t_AC (DLL Off). Data moves from the DRAM cell to the
sense amp and is held in a buffer waiting for the appropriate clock cycle. The data will fire from the buffer t_AC(DLL off)
after the clock edge prior to the programmed CAS latency.
Rev. 1.2 /June. 2008
24