HY5FS123235AFCP Datasheet, PDF (20/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
CK#
CK
Command
ACT
A0-A12 Row x
NOP
Row x
ACT
Row y
NOP
Row y
NOP
RD/WR
NOP
Col y
Col y
BA0-BA2
BA x
tRRD
BA y
tRCD
BA y
Figure 9: Bank Activation Command Cycle
= Donst Care
Data Terminator Disable
Bus snooping for READ commands other than CS# is used to control the on-die termination in the dual load
configuration. See Section DRIVER & TERMINATION for more details on GDDR4 SDRAM Termination.
Bank Restrictions
For eight bank GDDR4 devices, there may be a need to limit the number of activates in a rolling window to ensure
that the instantaneous current supplying capability of the devices is not exceeded. To reflect the true capability of the
DRAM instantaneous current supply, the parameter t_FAW (four activate window) is defined. No more than 4 banks may
be activated in a rolling t_FAW window. Converting to clocks is done by dividing t_FAW (ns) by t_CK (ns) and rounding up to
next integer value.
As an example of the rolling window, if (t_FAW/t_CK) rounds up to 10 clocks, and an activate command is issued in clock
N, no more than three further activate commands may be issued in clocks N+1 through N+9.
It is also acceptable and preferable that GDDR4 SDRAMs have no restrictions on the number of banks activated.
T0
T1
T2
T3
CK#
CK
Tm Tm+1 Tm+2 Tm+3 Tm+4
CMD ACT ACT ACT ACT
ACT ACT ACT ACT
t_RRD
t_RRD
t_RRD
t_FAW
t_FAW+3*t_RRD
t_RRD
t_RRD
t_RRD
Figure 10: tFAW
Rev. 1.2 /June. 2008
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