HY5FS123235AFCP Datasheet, PDF (7/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Table 1
Address and Control Termination Values
VALUE OHMS
CKE#
A0
60
L
H
120
H
H
240
H
L
RFU
L
L
VDD
VDDQ
VREF
CK#
CK
T0 T1 T2 T3 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Td0 Td1 Te0 Te1 Tf0 Tf1 Tg0 Tg1
RESET
CKE#
A0
CS#, RAS#,
CAS#, WE#
tATS tATH
tATS tATH
tCH tCL
CODE CODE CODE CODE CODE CODE CODE CODE
RA RA
tIS tIH
NOP NOP PRE NOP MRS NOP MRS NOP MRS NOP MRS NOP AR NOP AR NOP ACT NOP
DM[0:3]
A9-A12
A2,A3,A7
A4
A8
BA0,BA1,BA2
A1,A5,A6
RDQS[0:3]
WDQS[0:3]
DQ[0-31]
T=200us
Power-up:
VDD and
CK stable
CODE CODE CODE CODE CODE CODE CODE CODE
ALL BANKS
tIS tIH
High
CODE CODE CODE CODE CODE CODE CODE CODE
BA0
=H
CODE
BA0
=L
CODE CODE CODE CODE CODE
High
High
RA RA
RA RA
BA RA
T=200us
tRP
tMRD
tMRD
tMRD
tMRD
Load Extended Load Extended Load Extended
Mode Register 3 Mode Register 2 Mode Register 1 _{Load Mode}
Register
tRFC
tRFC
tDL
DONsT CARE
Figure 2 : GDDR4 SDRAM Initialization
Rev. 1.2 /June. 2008
7