HY5FS123235AFCP Datasheet, PDF (67/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
To ensure that the target impedance is achieved the POD I/O cell is designed to be calibrated to an
external 1% precision resistor.
The following procedure can be used to calibrate the cell:
1.) First calibrate the PMOS device against a 240 Ohm resister to VSS via the ZQ pin as illustrated in Figure 42.
• Set Strength Control to minimum setting
• Increase drive strength until comparator detects data bit is greater than VDDQ/2
• PMOS device is calibrated to 240 Ohms
2.) Then calibrate the NMOS device against the calibrated 240 Ohm PMOS device as illustrate in Figure 43.
• Set Strength Control to minimum setting
• Increase drive strength until comparator detects data bit is less than VDDQ/2
• NMOS device is now calibrated to 240 Ohms
VDDQ
Strength control [2:0]
3
Com parator
M atch
V D D Q /2
W h en M atch PM O S leg is calibrated to 2 4 0 oh m s
Figure 42: PMOS Calibration
M a tch
Rev. 1.2 /June. 2008
C a lib ra te d P M O S S tre n g th
C o m p a ra to r
V D D Q /2
S tre n g th co n tro l [2 :0 ]
Figure 43: NMOS Calibration
240 Ohms
VSSQ
VDDQ
3
3
VSSQ
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