HY5FS123235AFCP Datasheet, PDF (40/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
Figure 27: a) Block Diagram For READS
Read Data
8 bit
8 bit
DQ
Load on Read
DC Optim izwd Or
First Data in Sequence = 1
8 bit
DQ
DM
C o m parator
> 4 bit difference
DM
DRAM Logic
8 bit
Read Data
Mem ory Controller Logic
Load on Read
Figure 27: b) Block Diagram For WRITES
Write Data
Load on Write
DC Optimizwd Or
First Data in Sequence = 1
8 bit
DQ
DM
Load on Write
Rev. 1.2 /June. 2008
8 bit
8 bit
DQ
Comparator
> 4 bit difference
DM
Memory Controller Logic
8 bit
Data to be Written into Memory Arry
DRAM Logic
40