HY5FS123235AFCP Datasheet, PDF (14/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
DRIVER Strengths/Termination
The Data Driver Impedance, DZ, is used to determine the value of the data drivers impedance. The Auto Calibration
option enables the Auto-Calibration functionality of the DRAM which controls the Pulldown-, Pullup-Driver Strength and
the Termination over process, temperature and voltage changes. The nominal option enables the factory setting for
the Pulldown, Pullup-Driver-Strength and for the Termination. The design target for the factory setting is 40Ohm
Pulldown, 60Ohm Pullup-Driver-Strength and 60/120Ohm for DQ-Termination, 60/120/240Ohm for CMD/ADD-
Termination with nominal process, voltage and temperature conditions. With the nominal option enabled,
Driver-Strength and Termination is expected to change with process, voltage and temperature variations.
AC timings are only guaranteed with Auto Calibration.
DQ Termination
DQ Termination is used in combination with Driver Strengths/Termination setting to define the value for the on-die
termination for the DQ, DM, and WDQS pins.
GDDR4 SDRAM’s DQ Termination supports values of 1/4 ZQ or 1/2 ZQ intended for a single-or-dual-loaded system.
DQ Termination is set with bits A2 and A3 during an MRS command to EMR. The ZQ value is controlled by the EMR
Driver Strengths/Termination setting.
The DQ Termination setting is also used to turn off the on-die termination on a GDDR4 SDRAM. If A3 & A2 is set 00,
all DQ, DM, WDQS and Command/Address terminators on the device are disabled. If A3 & A2 is set 01 all DQ, DM,
WDQS Terminations are switched off but Command/Address terminators are still enabled. GDDR4 adds a mode where
only the DQS termination is on(see EMR3 LPTERM). The LPTERM mode is only valid if A3 & A2 is set to either 10 or 11.
To assure that address/command termination is enabled during initialization, the GDDR4 SDRAM automatically sets
EMR bits A3 & A2 and EMR3 bit A5 to a default setting during the 200 us window after power/clock stabilization.
The default setting for EMR[A3:A2] is either 01, 10 or 11, and for EMR3[A5] is 0.
Preamble
The READ and WRITE preamble in GDDR4 SDRAMs is programmable using bits A4 - A6. Values of 1-5 t_CK are
specified. Additional cycles of preamble may be required to attain the desired frequency. It is recommended that
Controller manufacturers support all values. Manufacturer datasheets should be consulted as the maximum number
of preamble cycles over clock frequency which is supported by the GDD4 SDRAm for Read commands is vendor
specific and will be defined by each vendor’s specification.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon
returning to normal operation after disabling the DLL for debugging or evaluation as well as low power operation.
(When the device exits self refresh mode in normal operation, the DLL is enabled automatically.) Any time the DLL is
enabled, t_DL must be met before a READ command can be issued.
DBI
Data Bus Inversion (DBI) for READ and WRITE is selected independently using bit A8 for read and bit A9 for write.
The mode of DBI is selected using bit A10. For more details on DBI see DBI in the Operation section.
Vendor ID
Vendor ID is used to identify the manufacture of the GDDR4 SDRAM. For more details on Vendor ID see Section
entitled VENDOR ID, PARITY & SCAN for more details.
Rev. 1.2 /June. 2008
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