HY5FS123235AFCP Datasheet, PDF (25/74 Pages) Hynix Semiconductor – 512M (16Mx32) GDDR4 SDRAM

HY5FS123235AFCP
T0
CK#
CK
COMMAND READ
ADDRESS
Bank a,
Col n
RDQS
T1
NOP
Col n
T13
T14 T14n T15 T15n T16 T16n T17 T17n T18
NOP
NOP
NOP
NOP
NOP
NOP
CL = 14
DQ
DOn
DO
n+7
t_{AC(DLL Off)}
DONsT CARE
Figure 15: DLL Off Timing
TRANSITIONING DATA
WRITE
WRITE bursts are initiated with a WRITE command (see Figure 16). The starting column and bank addresses are
provided at the WRITE command and the following clock cycle, and auto precharge is either enabled or disabled for
that access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the completion of
the burst or after t_RAS min is met or after the number of clock cycle programmed in EMR3 for RAS depending on the
implementation choice per DRAM vendor.
During WRITE bursts, the first valid data-in element will be registered on a rising of WDQS following the write latency
plus the number preamble set in the mode (and extended mode) register and subsequent data elements will be
registered on successive edges of WDQS. Prior to the first valid WDQS edge a cycle or cycles is/are needed and
specified as the WRITE Preamble. The cycle on WDQS following the last data-in element is known as the write
postamble and must be driven high by the controller it can not be left to float high using the on die termination.
A Valid strobe edge is defined as a strobe edge associated with data.
The time between the WRITE command and the first valid edge of WDQS (t_DQSS) is specified relative to the write
latency and the number of write preamble (WL - 0.25CK and WL + 0.25CK), where WPRE is the number of write
preamble set in the extended mode register. All of the WRITE diagrams show the nominal case, and where the two
extreme cases (i.e., t_DQSS [MIN] and t_DQSS[MAX]) might not be intuitive, they have also been included.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High and any
additional input data will be ignored. Data for any WRITE burst may not be truncated with a subsequent WRITE com-
mand. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command
assuming the previous burst has completed. The new WRITE command should be issued at least 4 cycles after the
first WRITE command. Data for any WRITE burst cannot be truncated by a subsequent PRECHARGE command.
After the PRECHARGE command, a subsequent command to the same bank cannot be issued until ^tRP is met.
The data inversion flag receives the RDQS signal to identify whether to store the true or inverted data. If RDQS is
HIGH, the data will be stored after inversion inside the GDDR4 SDRAM and not inverted when it recognizes RDQS is
LOW. WRITE Data Inversion can be programmed as an Disable(A9=0) or Enable (A9=1) in the EMRS.
Rev. 1.2 /June. 2008
25