MC908KX2MDWE Datasheet, PDF (94/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

External Interrupt (IRQ)
The vector fetch or software clear and the return of the IRQ1 pin to logic 1 can occur in any order. The
interrupt request remains pending as long as the IRQ1 pin is at logic 0. A reset will clear the latch and the
MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge sensitive only. With MODE1 clear, a vector fetch or
software clear immediately clears the IRQ1 latch.
The IRQF1 bit in the ISCR can be used to check for pending interrupts. The IRQF1 bit is not affected by
the IMASK1 bit, which makes it useful in applications where polling is preferred.
Use the branch if interrupt pin is high (BIH) or branch if interrupt pin is low (BIL) instruction to read the
logic level on the IRQ1 pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
8.5 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has these functions:
• Shows the state of the IRQ1 interrupt flag
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt request
• Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
Read:
Write:
Reset:
$001D
Bit 7
6
5
4
3
2
1
0
0
0
0
IRQF1
0
IMASK1
R
R
R
R
R
ACK1
0
0
0
0
U
0
0
R
= Reserved
U = Unaffected
Figure 8-3. IRQ Status and Control Register (ISCR)
Bit 0
MODE1
0
IRQF1 — IRQ1 Flag Bit
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as 0. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
94
Freescale Semiconductor