MC908KX2MDWE Datasheet, PDF (69/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Functional Description
7.3.1 Clock Enable Circuit
The clock enable circuit is used to enable the internal clock (ICLK) or external clock (ECLK) and the port
logic which is shared with the oscillator pins (OSC1 and OSC2). The clock enable circuit generates an
ICG stop (ICGSTOP) signal which stops all clocks (ICLK, ECLK, and the low-frequency base clock,
IBASE). ICGSTOP is set and the ICG is disabled in stop mode if the oscillator enable in stop
(OSCENINSTOP) bit in the CONFIG (or MOR) register is clear. The ICG clocks will be enabled in stop
mode if OSCENINSTOP is high.
The internal clock enable signal (ICGEN) turns on the ICG which generates ICLK. ICGEN is set (active)
whenever the ICGON bit is set and the ICGSTOP signal is clear. When ICGEN is clear, ICLK and IBASE
are both low.
The external clock enable signal (ECGEN) turns on the external clock generator which generates ECLK.
ECGEN is set (active) whenever the ECGON bit is set and the ICGSTOP signal is clear. ECGON cannot
be set unless the external clock enable (EXTCLKEN) bit in the CONFIG (or MOR) register is set. When
ECGEN is clear, ECLK is low.
The port B6 enable signal (PB6EN) turns on the port B6 logic. Since port B6 is on the same pin as OSC1,
this signal is only active (set) when the external clock function is not desired. Therefore, PB6EN is clear
when ECGON is set. PB6EN is not gated with ICGSTOP, which means that if the ECGON bit is set, the
port B6 logic will remain disabled in stop mode.
The port B7 enable signal (PB7EN) turns on the port B7 logic. Since port B7 is on the same pin as OSC2,
this signal is only active (set) when two-pin oscillator function is not desired. Therefore, PB7EN is clear
when ECGON and the external crystal enable (EXTXTALEN) bit in the CONFIG (or MOR) register are
both set. PB6EN is not gated with ICGSTOP, which means that if ECGON and EXTXTALEN are set, the
port B7 logic will remain disabled in stop mode.
7.3.2 Internal Clock Generator
The ICG, shown in Figure 7-2, creates a low frequency base clock (IBASE), which operates at a nominal
frequency (f_NOM) of 307.2 kHz ± 25%, and an internal clock (ICLK) which is an integer multiple of IBASE.
This multiple is the ICG multiplier factor (N), which is programmed in the ICG multiplier register (ICGMR).
The ICG is turned off and the output clocks (IBASE and ICLK) are held low when the ICG enable signal
(ICGEN) is clear.
The ICG contains:
• A digitally controlled oscillator
• A modulo "N" divider
• A frequency comparator, which contains voltage and current references, a frequency to voltage
converter, and comparators
• A digital loop filter
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
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