MC908KX2MDWE Datasheet, PDF (23/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Chapter 2
Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space.
The memory map, shown in Figure 2-1, includes:
• 7680 bytes of FLASH memory
• 192 bytes of random-access memory (RAM)
• 36 bytes of user-defined vectors
• 295 bytes of monitor read-only memory (ROM)
2.2 I/O Registers
Most of the control, status, and data registers are in the zero-page area of $0000–$003F. Additional
input/output (I/O) registers have the following addresses:
• $FE01 — SIM reset status register, SRSR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
• $FF7E — FLASH block protect register, FLBPR
in non-volatile FLASH memory
• $FFFF — COP control register, COPCTL
A summary of the available registers is provided in Figure 2-2. Table 2-1 is a list of vector locations.
2.3 Monitor ROM
The 295 bytes at addresses $FE20–$FF46 are reserved ROM addresses that contain the instructions for
the monitor functions.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
23