MC908KX2MDWE Datasheet, PDF (86/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Internal Clock Generator Module (ICG)
Addr. Register Name
Bit 7
6
5
4
3
2
1
ICG DCO Divider Control ^Read:
DDIV3
DDIV2
DDIV1
$0039
Register (ICGDVR) Write:
See page 89. _Reset:
0
0
0
0
U
U
U
$003A
ICG DCO Stage Control ^Read:
Register (ICGDSR) Write:
See page 89. _Reset:
DSTG7
R
U
DSTG6
R
U
DSTG5
R
U
DSTG4
R
U
DSTG3
R
U
DSTG2
R
U
DSTG1
R
U
= Unimplemented
R
= Reserved U = Unaffected
Figure 7-10. ICG Module I/O Register Summary (Continued)
Bit 0
DDIV0
U
DSTG0
R
U
Table 7-5. ICG Module Register Bit Interaction Summary
Condition
Register Bit Results for Given Condition
CMIE CMF CMON CS ICGON ICGS ECGON ECGS N[6:0] TRIM[7:0] DDIV[3:0] DSTB[7:0]
Reset
00
00 1
0
0
0 $15
$80
—
—
OSCENINSTOP = 0,
STOP = 1
0
0
0 ——
0
—
0
—
—
—
—
EXTCLKEN = 0
00
00 1
—
0
0
—
—
uw
uw
CMF = 1
— (1) 1 — 1
—
1
— uw
uw
uw
uw
CMON = 0
0
0 (0) — —
—
—
——
—
—
—
CMON = 1
— — (1) — 1
—
1
— uw
uw
uw
uw
CS = 0
— — — (0) 1
—
—
——
—
uw
uw
CS = 1
— — — (1) — —
1
——
—
—
—
ICGON = 0
00
0 1 (0)
0
1
——
—
—
—
ICGON = 1
— — — — (1) —
—
——
—
uw
uw
ICGS = 0
us — us uc — (0) —
——
—
—
—
ECGON = 0
00
00 1
— (0)
0
—
—
uw
uw
ECGS = 0
us — us us —
—
—
(0) —
—
—
—
IOFF = 1
— 1* (1) 1 (1) 0
(1)
— uw
uw
uw
uw
EOFF = 1
— 1* (1) 0 (1) — (1)
0 uw
uw
uw
uw
N = written
(0) (0) (0) — —
0*
—
——
—
—
—
TRIM = written
(0) (0) (0) — —
0*
—
——
—
—
—
—Register bit is unaffected by the given condition.
0, 1Register bit is forced clear or set (respectively) in the given condition.
0*, 1*Register bit is temporarily forced clear or set (respectively) in the given condition.
(0), (1)Register bit must be clear or set (respectively) for the given condition to occur.
us, uc, uwRegister bit cannot be set, cleared, or written (respectively) in the given condition.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
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Freescale Semiconductor