MC908KX2MDWE Datasheet, PDF (81/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Usage Notes
7.4.4.3 Variable-Delay Ring Oscillator
The variable-delay ring oscillator’s period is adjustable from 17 to 31 stage delays, in increments of two,
based on the upper three DCO stage control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17
stage delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45%
to 11.8% effect on the output frequency. This also corresponds to the size correction made when the
frequency error is greater than ±15%. The value of the binary weighted divider does not affect the relative
change in output clock period for a given change in DSTG[7:5].
7.4.4.4 Ring Oscillator Fine-Adjust Circuit
The ring oscillator fine-adjust circuit causes the ring oscillator to effectively operate at non-integer
numbers of stage delays by operating at two different points for a variable number of cycles specified by
the lower five DCO stage control bits (DSTG[4:0]). For example, when DSTG[7:5] is %011, the ring
oscillator nominally operates at 23 stage delays. When DSTG[4:0] is %00000, the ring will always operate
at 23 stage delays. When DSTG[4:0] is %00001, the ring will operate at 25 stage delays for one of 32
cycles and at 23 stage delays for 31 of 32 cycles. Likewise, when DSTG[4:0] is %11111, the ring operates
at 25 stage delays for 31 of 32 cycles and at 23 stage delays for one of 32 cycles. When DSTG[7:5] is
%111, similar results are achieved by including a variable divide-by-two, so the ring operates at 31 stages
for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the
remainder of the cycles. Adjusting the DSTG[0] bit has a 0.202% to 0.368% effect on the output clock
period. This corresponds to the minimum size correction made by the DLF, and the inherent, long term
quantization error in the output frequency.
7.4.5 Switching Internal Clock Frequencies
The frequency of the internal clock (ICLK) may need to be changed for some applications. For example,
if the reset condition does not provide the correct frequency, or if the clock is slowed down for a low power
mode (or sped up after a low-power mode), the frequency must be changed by programming the internal
clock multiplier factor (N). The frequency of ICLK is N times the frequency of IBASE, which is 307.2 kHz
± 25%.
Before switching frequencies by changing the N value, the clock monitor must be disabled. This is
because when N is changed, the frequency of the low-frequency base clock (IBASE) will change
proportionally until the digital loop filter has corrected the error. Since the clock monitor uses IBASE, it
could erroneously detect an inactive clock. The clock monitor cannot be re-enabled until the Internal Clock
is stable again (ICGS is set).
The following flow is an example of how to change the clock frequency:
• Verify there is no clock monitor Interrupt by reading the CMF bit
• Turn off the clock monitor
• If desired, switch to the external clock (see 7.4.1 Switching Clock Sources)
• Change the value of N
• Switch back to internal (see 7.4.1 Switching Clock Sources), if desired
• Turn on the clock monitor (see 7.4.2 Enabling the Clock Monitor), if desired
7.4.6 Nominal Frequency Settling Time
Because the clock period of the internal clock (ICLK) is dependent on the digital loop filter outputs (DDIV
and DSTG) which cannot change instantaneously, ICLK will temporarily operate at an incorrect clock
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
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